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Gigabyte MZ31-AR0-00 EPYC Server Motherboard

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The Gigabyte MZ31-AR0-00 is an E-ATX single-socket AMD EPYC (SP3 / LGA 4094) server motherboard. Three board revisions cover Naples, Rome, and Milan CPU generations. The distinguishing feature is I/O density: 16 SATA ports via SlimSAS, dual SFP+ 10GbE (Broadcom BCM57810S), 16 DIMM slots (up to 2 TB), and 7 PCIe 3.0 expansion slots. No other single-socket EPYC board has both 16 DIMMs and 16 SATA ports.

Manufactured by Gigabyte Technology (Taiwan), server/enterprise division. In production from approximately 2017 through 2023 across three revisions.

Specifications

Component Detail
CPU Single Socket SP3 (LGA 4094). Rev 1.x: EPYC 7001 (Naples). Rev 2.x: EPYC 7001 + 7002 (Naples + Rome). Rev 3.x: EPYC 7002 + 7003 (Rome + Milan).
Memory 16× DDR4 DIMM (8-channel, 2 DIMMs per channel). RDIMM, LRDIMM (ECC). Max: 2 TB (LRDIMM). Speeds: 2666 MT/s (Naples 1DPC), 3200 MT/s (Rome/Milan 1DPC). 2DPC reduces speed by one step.
PCIe 4× PCIe 3.0 x16 + 2× PCIe 3.0 x8 + 1× PCIe 3.0 x16 (wired x8). 88 lanes to expansion slots. Bifurcation settings exist in BIOS but are reported unreliable/non-functional. PCIe 3.0 only, even with Rome/Milan CPUs.
Storage 16× SATA 3.0 via 4× SlimSAS (SFF-8654) connectors. 1× M.2 (PCIe 3.0 x4). No 7-pin SATA headers. No SATA DOM.
Networking 2× SFP+ 10GbE (Broadcom BCM57810S). 1× 1GbE RJ-45 (dedicated BMC/IPMI).
BMC ASPEED AST2500. AMI MegaRAC SP-X (replaced earlier Vertiv/Avocent firmware). IPMI 2.0, HTML5 KVM, virtual media, SOL. No license fees for full KVM — unlike HP iLO, Dell iDRAC, or Lenovo XClarity.
Fan headers 7× 4-pin (2 CPU + 5 chassis)
Power 24-pin ATX + 2× 8-pin EPS 12V
Display VGA via BMC (AST2500 integrated)
Form factor E-ATX (305 × 330 mm). Larger than standard ATX — verify chassis compatibility.
Manufacturer Gigabyte Technology (Taiwan), Server/Enterprise Division

Board revisions

Revision CPU support BIOS series Flash chip Introduced
Rev 1.x Naples (EPYC 7001) F-series (F03–F22) 16 MB SOP8 ~2017
Rev 2.x Naples + Rome (7001 + 7002) R-series with F suffix (R03_F16–R34_F22) 32 MB SOP8 ~2019
Rev 3.x Rome + Milan (7002 + 7003) R-series + M-series (R22–R34) 32 MB SOP8 ~2021

The revision number is printed on the PCB. The only hardware difference between revisions is the BIOS flash chip size and factory-loaded firmware. This means Rev 1.x boards can run Rome or Milan CPUs with a flash chip upgrade or selective ROM flashing (see Cross-revision CPU upgrade).

BIOS

Rev 1.x — F-series (Naples only)

Version Approx. date AGESA Notes
F03 2017 (shipped) NaplesPI early Only confirmed stable BIOS. Ships from factory.
F04 2017–2018 NaplesPI early Bricking confirmed — Phoronix reviewer could not boot after flashing.
F05 2018 NaplesPI early Reported unbootable on some systems.
F06 2018 NaplesPI early Bricking confirmed — same result as F04 per Phoronix.
F07b 04/02/2018 NaplesPI 1.0.0.6 Confirmed AGESA via AMD-SEV GitHub issue #32. Hetzner AX160-NVME deployed this version at scale. SEV API 0.16.
F09 2018–2019 NaplesPI 1.0.0.7 Stability improvements.
F12–F16 2019–2020 NaplesPI 1.0.0.8 Security patches (BootHole CVE era).
F20 2020 NaplesPI 1.0.0.A (est.) BootHole (GRUB2 secure boot bypass) mitigations.
F22 2020–2021 NaplesPI 1.0.0.B (est.) Final Rev 1.x BIOS. Naples only.

Community verdict: F03 is universally stable. F04 through F06 should be avoided. F07b is the next safe target. Many long-term Naples users stay on F03 or F07b — the F04–F06 bricking was never publicly explained by Gigabyte.

Rev 2.x — R-series (Naples + Rome)

Version Approx. date AGESA (Rome) Notes
R03_F16 ~2019 RomePI 1.0.0.2 Initial Rome support. Required for EPYC 7002 ES processors.
R04–R06 2019–2020 RomePI 1.0.0.2–4 PCIe error fixes (Gigabyte Security Advisory 1740).
R20_F19 03/27/2020 RomePI 1.0.0.6 AGESA update. CVE mitigations begin.
R27_F20 08/24/2020 RomePI 1.0.0.8 Updated Redfish protocol. Boot option fixes.
R28_F20 10/12/2020 RomePI 1.0.0.8–A Secure boot update for BootHole (GRUB2 bypass).
R34_F22 07/12/2021 RomePI 1.0.0.D Latest Rev 2.x BIOS. Security-patched.

Recommended: R34_F22 for production Rome deployments.

Rev 3.x — R/M-series (Rome + Milan)

Warning: Rev 3.x drops Naples support. Flashing Rev 3.x on a Naples system results in a permanent brick without hardware programmer recovery.

Version Approx. date AGESA Notes
R22 ~2021 RomePI 1.0.0.8 + MilanPI 1.0.0.0 Initial Milan support.
R24–R26 2021 RomePI 1.0.0.9 + MilanPI 1.0.0.x Naples dropped from this point forward.
R28 2022 RomePI 1.0.0.9 + MilanPI 1.0.0.8 Security and stability updates.
R34 2022–2023 RomePI 1.0.0.D + MilanPI 1.0.0.E Latest known Rev 3.x BIOS.

Rev 3.x BIOS packages contain three separate 16 MB flashable files: flash_F.rom (Naples), flash_R.rom (Rome), flash_M.rom (Milan). This structure allows selective per-generation flashing.

Post-flash critical settings

These reset to defaults after every BIOS update:

  • IOMMU: AMD CBS → NBIO Common Options → NB Configuration → IOMMU. Set to "Enabled" for Proxmox, KVM, or any PCIe passthrough workload. This path is not in the standard menu — navigate through CBS.
  • SR-IOV: Advanced → PCI Subsystem Settings → SR-IOV Support. Default: Disabled.
  • ACS: AMD CBS → NBIO Common Options. Enable for proper IOMMU group isolation.
  • AER: Same path. Enable explicitly for SR-IOV.

BIOS recovery

Jumper Code Function
CLR_CMOS J1 1-2: Normal. 2-3: Clear CMOS.
BIOS_PWD J4 1-2: Normal. 2-3: Skip supervisor password.
BIOS_RCVR J5 1-2: Normal. 2-3: BIOS recovery mode.

The board does NOT have traditional Gigabyte DualBIOS (two separate chips with automatic failover). The J5 recovery jumper resolved the "ROM Image is not loaded / ROM Image updated denied" error for some users. For completely unresponsive boards, a CH341A SPI programmer with SOIC-8 clip can read and rewrite the SOP8 flash chip directly. The chip operates at 3.3V — no voltage adapter needed.

BMC (ASPEED AST2500)

Capabilities

IPMI 2.0 remote management with HTML5 KVM (newer firmware), virtual media, SOL (Serial over LAN), and remote power control. Earlier firmware used a Java-based Avocent/Vertiv KVM interface; AMI MegaRAC SP-X firmware replaces it with HTML5. Full KVM functionality is available without licensing fees.

Factory default credentials: admin / motherboard serial number (printed on a sticker on the board, not "admin" or "password"). After BMC firmware updates, the password resets to the serial number. Used boards from China may lack the sticker.

BMC firmware transition

The board shipped with Vertiv (Avocent) BMC firmware and transitioned to AMI MegaRAC SP-X. When updating BMC firmware, use the -no-reboot flag or the BMC may brick. Firmware is available from Gigabyte: AST2500 AMI 12.x.

Security vulnerabilities

Advisory Severity Description Status
Gigabyte SA-2217 CVSS 10.0 AMI MegaRAC authentication bypass. Actively exploited per CISA (March 2025). URGENT. Patches released March 2025. Any MZ31-AR0 running AMI BMC firmware is affected.
Gigabyte SA-1680 ("Pantsdown") CVSS 9.8 AST2500 arbitrary read/write from host CPU to BMC. Fixed in firmware updates.

Networking (Broadcom BCM57810S)

Dual SFP+ 10GbE using the Broadcom BCM57810S controller. Linux driver: bnx2x (in-kernel, no proprietary driver needed). Supports SR-IOV for virtual function assignment in virtualization environments.

SFP+ ports accept standard modules: SR (multimode fiber), LR (single-mode fiber), DAC (Direct Attach Copper) cables, and SFP+ to RJ45 copper transceivers. Does NOT support 25G — the BCM57810S is 10G-only.

No fallback 1GbE RJ45 data port. The only RJ-45 port is the dedicated BMC management NIC. If your switch does not support SFP+, you need an add-in NIC.

Memory

8-channel DDR4 with 16 DIMM slots. Supports RDIMM and LRDIMM with ECC. Unbuffered desktop DDR4 is not compatible.

Population rules:

  • Do NOT mix RDIMM and LRDIMM
  • Do NOT mix x4 and x8 DIMMs within the same channel
  • Populate across all 4 NUMA nodes — putting all DIMMs on one side leaves 2 nodes without local memory and destroys performance
  • Population order: A1, B1, C1, D1, E1, F1, G1, H1 (one per channel first)
  • 8 DIMMs (one per channel) is the sweet spot — runs at full rated speed
  • 16 DIMMs (all slots populated) limits speed to DDR4-2133 regardless of DIMM rating

Memory population directly affects PCIe stability. Users report inconsistent PCIe link speeds with fewer than 8 channels populated.

PCIe and expansion

128 PCIe 3.0 lanes from the EPYC CPU. 88 lanes routed to 7 expansion slots, remaining lanes serve onboard controllers (SlimSAS, M.2, 10GbE, BMC).

Slot Physical Electrical Notes
1 x16 x16 Full PCIe 3.0 x16
2 x8 x8 PCIe 3.0 x8
3 x16 x16 Full PCIe 3.0 x16
4 x16 x16 Full PCIe 3.0 x16
5 x16 x8 Physical x16, electrical x8
6 x16 x16 Full PCIe 3.0 x16
7 x8 x8 PCIe 3.0 x8

Physical clearance: The top 4 PCIe slots sit behind 8 DIMM sockets. Full-length double-width GPUs will not fit in these slots without riser cables. Only the bottom slots accept full-length cards directly. One community member summarized: "Of the theoretical 5 PCIe x16 slots you may have thought you could put a full size graphics card into — only one physically fits. ONE."

Bifurcation: BIOS includes bifurcation settings (x4x4, x8x8, x4x4x4x4, etc.), but Level1Techs confirmed these are non-functional or not exposed in many BIOS versions. The related MZ32-AR0 (dual socket) is described as "very buggy" with bifurcation. Use PLX/Broadcom PCIe switch cards for NVMe splitting instead.

PCIe generation: Strictly PCIe 3.0 on all revisions. Even with Rome or Milan CPUs that support PCIe 4.0 natively, the board limits to Gen 3.

PCIe slot issues (odd/even pattern)

A known failure pattern: odd-numbered slots (1, 3, 5) work while even-numbered slots (2, 4) produce errors, particularly with SAS/HBA controllers. Ranked diagnosis:

  1. BIOS/AGESA bug — most likely. Specific AGESA versions have PCIe register corruption issues. Gigabyte issued Security Advisory 1740 for a Rome-specific silicon erratum (Erratum #1185), but Naples AGESA versions also have documented PCIe initialization bugs.
  2. Die-level routing — Naples uses 4 Zeppelin dies, each with 32 lanes. Odd and even slots may route to different dies; a defective die or die-pair would affect specific slot groups.
  3. Memory population — partial memory population causes inconsistent PCIe link speeds. All 8 channels should be populated.
  4. Power delivery — less likely but possible on aging boards.

Before replacing the board: Try updating BIOS/AGESA, populate all 8 memory channels, test with a different card type, and check dmesg | grep -i "pci\|aer\|error" for specific error signatures.

Storage

16 SATA 3.0 ports via 4 SlimSAS (SFF-8654) connectors. Each connector carries 4 SATA lanes. The board ships with 2 SlimSAS-to-SATA breakout cables.

These are SATA only, not SAS — despite the SlimSAS connector name. SAS drives will not work on the onboard ports. For SAS, install an HBA in a PCIe slot.

No 7-pin SATA headers. No SATA DOM. Use the M.2 slot for OS/boot.

SATA passthrough in Proxmox/KVM

Passing through the onboard AMD FCH SATA controller (PCI ID 1022:7901) causes the system to hang. The controller does not implement Function Level Reset (FLR) properly.

Fix (kernel 5.15+): echo bus > /sys/bus/pci/devices/0000:83:00.0/reset_method

Replace the PCI address with the actual address of your SATA controller. Persist across reboots via a hookscript, crontab, or systemd unit. One user noted passing through the second SATA controller affected the first on the host — test your configuration.

Cross-revision CPU upgrade

Rev 1.x boards can run Rome or Milan CPUs. The ONLY hardware difference between revisions is the BIOS flash chip and factory firmware.

Procedure (no soldering required in most cases):

  1. Download the Rev 3.x BIOS package from Gigabyte's support page
  2. Extract flash_R.rom (for Rome) or flash_M.rom (for Milan) — each is exactly 16 MB
  3. Flash to the existing 16 MB chip using a CH341A programmer with SOP8 clip

The BMC has a BIOS signature check that blocks cross-revision flashing via the web interface. Hardware programmer bypasses this entirely. RBU-to-BIN conversion: remove the last 16 bytes from an .RBU file to get a raw flashable image.

Confirmed working: Multiple users on ServeTheHome confirmed Rome on Rev 1.1 boards. Milan on Rev 1.x is theoretically possible but lacks confirmed community reports.

Failure modes: Flashing a Naples-only BIOS (F20B/F20D) onto a board running Rome = permanent brick + BMC access loss. Old used Rev 1.0 boards from China (ex-OEM) may not work for cross-flashing. Always back up the existing chip before flashing.

Fan control

Gigabyte server BMC fan control is limited compared to Supermicro. The BMC reportedly ignores custom fan profile requests. No IPMI raw fan control commands have been reverse-engineered for Gigabyte EPYC boards (unlike Supermicro's well-documented ipmitool raw 0x30 0x70 0x66).

Community consensus: Use physically quiet fans (Noctua NF-A12x25) rather than trying to control fan speed through BMC software.

Virtualization (Proxmox, KVM, ESXi)

Each onboard SATA controller occupies its own IOMMU group. PCIe slots are in separate groups, unlike consumer AM4 boards where root complexes bundle multiple slots together.

128 PCIe lanes means a single-socket system can pass through GPUs, NVMe drives, and SATA controllers to different VMs without lane contention.

Required BIOS settings: Enable IOMMU (AMD CBS → NBIO → NB Configuration → IOMMU), add amd_iommu=on iommu=pt to kernel cmdline. Enable ACS for proper group isolation.

The BCM57810S supports SR-IOV for virtual NIC assignment.

Known issues

Hardware

  • Only 1 slot fits full-length GPUs directly — slots 4–7 sit behind DIMM banks. Use riser cables or VLP memory for clearance.
  • No VRM heatsink — 6-phase VRM relies entirely on chassis airflow. Problematic with 180W+ CPUs in non-server or open-bench cases. Add aftermarket VRM heatsinks if needed.
  • No SATA DOM — use M.2 NVMe for OS boot.
  • No fallback 1GbE data port — only SFP+ for data networking. If your switch lacks SFP+, you need an add-in NIC.
  • E-ATX form factor — does not fit most consumer ATX cases.
  • No POST with non-ECC UDIMM — board requires ECC RDIMM or LRDIMM. Consumer DDR4 results in fans spinning, no video, no beep codes. No error indication at all.
  • 16 DIMMs populated halves memory speed to DDR4-2133 regardless of DIMM rating. 8 DIMMs (1 per channel) runs at full rated speed.
  • VSOC_DUAL 0V error — BMC reports 0V, board fails to POST. At least one Rev 1.x report (2024). No documented fix — likely requires RMA.
  • ~71 second POST time — partially reducible by disabling unused onboard controllers in BIOS (~62s).

BIOS

  • BIOS updates frequently brick the board — F04, F05, F06 are confirmed unbootable on Rev 1.x. Phoronix reviewer could not get past F03. If updating: backup current BIOS first via CH341A programmer, target a known-good version, have recovery hardware ready.
  • "ROM Image is not loaded / ROM Image updated denied" — board enters BIOS setup instead of booting OS at every start. Fix: set BIOS recovery jumper (J5) to pins 1-2. Permanent fix.
  • BIOS flash can block specific CPUs — after a failed flash, board refuses to POST with the installed CPU but works with a different one. Boot with alternate CPU, reflash, swap back.
  • Legacy boot disables VGA output — CSM/Legacy mode produces no video (onboard or add-in). AST2500 VGA requires UEFI GOP driver. Always use UEFI boot mode.
  • Legacy VGA selection menu disappeared in F07+ — F06 had a menu for selecting onboard vs external GPU display. F07 and later emptied this menu.
  • PCIe 3.0 only — even with Rome/Milan CPUs that natively support Gen 4.
  • Bifurcation broken/unreliable — settings either missing, hidden, or non-functional depending on BIOS version. Use PLX-based switch cards for NVMe splitting.
  • RAM timing control removed in F20+ — per-channel timing settings removed. Stay on earlier BIOS if per-channel tuning is needed.
  • WHEA Internal Error 0x122 on Windows — BSOD on hot restarts (warm reboots). Cold boots work. Fix: BIOS F09 or later AND apply KB4057142 to install.wim/boot.wim. Use cold shutdowns during initial Windows setup.

BMC / IPMI

  • Vertiv-to-AMI BMC firmware transition can brick BMC — standard flash procedure bricks BMC on Rev 1.0 boards. Must use -no-reboot flag, then full AC power removal. FRU data will be lost (backup first).
  • BMC password lockout — default credentials fail after certain firmware updates. Recovery: try admin/board-serial-number, try admin/password, then ipmitool user set password via local access if needed. Used boards from China may lack the serial number sticker.
  • BIOS update via BMC is unreliable — BMC signature check blocks cross-revision BIOS files. Flash mechanism may corrupt BIOS chip. Use CH341A hardware programmer for Rev 1.x.
  • BMC fan control non-functional — ignores custom fan profile requests. No IPMI raw fan commands have been reverse-engineered for Gigabyte EPYC boards (unlike Supermicro). Use physically quiet fans (Noctua NF-A12x25).

PCIe

  • PCIe speed negotiation cycling — reported with dual RTX 3090: link speeds cycle between Gen1/Gen2/Gen3. No BIOS option to lock generation. Workaround: kernel parameter pcie_aspm=off.
  • RTX 2080 incompatibility — triggers "error 9c" at boot on Rev 1.x. GTX 1080 works in the same slot. Likely BIOS PCIe initialization incompatibility with Turing architecture.
  • Slot-to-die mapping never published — Gigabyte never documented which slots connect to which CPU dies. Required for NUMA-aware PCIe device placement. Map on a live system with lspci -tv and NUMA node checks.

Operational

  • Gigabyte server support is slow — 2-month replacement cycles reported. Community forums (ServeTheHome, Level1Techs) are more useful than official support.
  • Documentation is minimal — no slot-to-die mapping, no detailed BIOS changelog, no fan control documentation. Community knowledge is the primary source.

Competitive position

Feature Gigabyte MZ31-AR0 ASRock EPYCD8-2T Supermicro H11SSL-i
Form factor E-ATX ATX ATX
DIMM slots 16 8 8
Max RAM 2 TB 1 TB 1 TB
Onboard 10G 2× SFP+ (BCM57810S) 2× RJ45 (Intel X550) None (1GbE only)
SATA ports 16 (SlimSAS) 8 8
PCIe slots 7 7 6
Bifurcation Broken Supported Supported
GPU clearance Poor Better Better
SATA DOM No Yes Yes
CPU gen support Naples/Rome/Milan* Naples/Rome Naples/Rome
License-free KVM Yes Yes Yes (Java-based)

* Rome/Milan on Rev 1.x requires flash chip modification.

The MZ31-AR0 has more memory slots, more SATA ports, and built-in 10GbE. The competitors fit in standard ATX cases, have working bifurcation, and better GPU physical clearance.

Market position

Niche but respected. Estimated low thousands to low tens of thousands of units across three revisions (2017–2023). Third in community adoption behind Supermicro H11SSL and ASRock EPYCD8-2T, but first in I/O density. German datacenters (Hetzner AX160-NVME) represent the largest known deployment. The board is still being purchased on the secondary market in 2026.

Secondary market pricing (2024–2026)

  • Board only: $100–200 USD
  • With Naples CPU: $150–300
  • With Rome CPU (pre-modded BIOS): $300–600
  • Cost per PCIe lane at $200: ~$1.56/lane
  • Cost per DIMM slot at $200: ~$12.50/slot

Typical builds

The 16 SATA ports make this a natural fit for NAS and storage servers running ZFS or TrueNAS. With dual 10GbE and up to 2 TB RAM for ARC cache, a complete storage build needs zero add-in cards. Virtualization hosts benefit from the 16 DIMMs when running many VMs that each need substantial memory. Multi-GPU compute builds work with riser cables in an open-air frame, giving 7 slots at x8/x16 bandwidth for around $200 in board cost. The flash mod also makes this one of the cheapest ways to run Rome or Milan CPUs — a $100 used Rev 1.x board plus a $5 programmer.

Noctua cooler compatibility

Community-confirmed compatible TR4-SP3 coolers (all fit without obstruction):

  • NH-U9 TR4-SP3 (125 mm height — fits 4U rack)
  • NH-U12S TR4-SP3 (mid-size)
  • NH-U14S TR4-SP3 (largest, 6 heatpipes)

The EPYC socket orientation on this board causes heatsink fans to blow left-to-right rather than front-to-back. Plan chassis airflow accordingly.

See also

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